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Board Components
The development board provides two separate methods for configuring
the FPGA:
1.
2.
Using the Quartus ? II software running on a host computer, a
designer configures the device directly via an Altera download
cable connected to the FPGA JTAG header (J24).
When power is applied to the board, a configuration controller
device (U3) attempts to configure the FPGA with hardware
configuration data stored in flash memory. For more information on
the configuration controller, refer to “Configuration Controller
f
Push-Button
Switches (SW0 -
SW3)
For Cyclone II-related documentation including pin out data for the
EP2C35 device, see the Altera Cyclone II literature page at
www.altera.com/literature/lit-cyc2.jsp .
SW0 – SW3 are momentary-contact push-button switches to provide
stimulus to designs in the FPGA. Refer to Figure 2–2 . Each switch is
connected to an FPGA general-purpose I/O pin with a pull-up resistor as
shown in Table 2–3 . Each I/O pin perceives a logic 0 when its
corresponding switch is pressed.
Figure 2–2. Push-Button Switches (SW0 – SW3)
D0
D1
D2
D3
D4
D5
D6
D7
SW0
SW1
SW2
SW3
Table 2–3. Push Button Switches Pin Table
SW0
SW1
SW2
SW3
Button
Y11
AA10
AB10
AE6
FPGA Pin
Board Net Name
user_pb0
user_pb1
user_pb2
user_pb3
2–4 Reference Manual
Nios Development Board Cyclone II Edition
Altera Corporation
May 2007
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